In a NAND flash memory, a data latch circuit that holds data transferred from a host or from memory cell transistors is connected to a sense amplifier by a common data bus with a large wiring line capacitance. The data latch circuit includes a switching element and two inverters. The two inverters employ a configuration in which the output terminals of the respective inverters are connected to the input terminals of the others, respectively, which is described in Jpn. Pat. Appln. KOKAI Publication No. 09-274527. Data held in the data latch circuit has a value corresponding to the potential of a wiring line connecting the inverters.
In writing, data is transferred from the data latch circuit to memory cell transistors through the sense amplifier. In reading, the sense amplifier reads data held in memory cell transistors and transfers the data to the data latch circuit.